The present invention relates to a technology of clock transmission in semiconductor integrated circuits.
In semiconductor integrated circuits, there are used in some cases a plurality of clocks that have the same frequency and retain a predetermined phase difference between the clocks. These clocks are collectively called a multi-phase clock. Conventionally, a multi-phase clock is generated and output by a clock generation circuit constructed of a phase locked loop (PLL) and the like. Clocks with different phases constituting a multi-phase clock are delivered to circuit blocks that require the multi-phase clock via transmission lines prepared exclusively for the respective clocks. One of such examples is disclosed in Japanese Laid-Open Patent Publication No.2-255908.
In the conventional multi-phase clock transmission method described above, in which multiple phase clocks are individually transmitted, m (m is an integer) lines are necessary for transmission of an m-phase clock. Therefore, as m is greater, a larger area is required for the transmission lines.
In general, as the distance of clock transmission is longer, the path length difference between the multiple phase clocks is greater, and also the influence of crosstalk with another signal line and the like is greater. As a result, the skew between the multiple phase clocks increases.
If the frequency of the multiple phase clocks is high, the proportion of the skew between the transmitted multiple phase clocks with respect to the clock period increases. In this event, the phase relationship between the multiple phase clocks may no more be secured in respective circuit blocks receiving the multi-phase clock, and this may cause malfunction of circuits.
An object of the present invention is providing a multi-clock transmission circuit and method in which the area for transmission lines required can be reduced and also the skew between multiple phase clocks can be reduced.
Specifically, the multi-phase clock transmission circuit of the present invention includes: a clock generator for generating a clock synchronizing with a reference clock and a control signal responsive to a phase difference between the reference clock and the clock and outputting the clock and the control signal; and a delay circuit for generating a multi-phase clock based on the clock and the control signal and outputting the multi-phase clock, wherein the clock generator comprises a clock generation circuit including a delay element for giving a delay according to the control signal to an input signal and outputting the resultant signal, the clock generation circuit generating a signal having a frequency equal to an integral multiple of a frequency of the reference clock and outputting the signal as the clock, and the delay circuit comprises a circuit receiving the clock and including a plurality of delay elements in cascade connection each giving a delay according to the control signal to an input signal and outputting the resultant signal, signals output from the plurality of delay elements being used as signals constituting the multi-phase clock.
According to the invention described above, only one clock is transmitted from the clock generator to the delay circuit, and the delay circuit generates a multi-phase clock. With this configuration, the number of transmission lines between the clock generator and the delay circuit can be reduced compared with the case that the clock generator generates a multi-phase clock and transmits the clock to the delay circuit. In addition, the phase difference between clocks constituting the multi-phase clock generated by the delay circuit can be kept constant irrespective of the length of the line for transmission of the clock. As a result, a circuit block having this delay circuit can use a multi-phase clock with reduced inter-block skew.
In the multi-phase clock transmission circuit described above, preferably, the clock generator further includes: a phase comparison circuit for comparing phases between the reference clock and the clock output from the clock generation circuit and outputting the comparison result; and a low-pass filter for outputting a low-frequency component of the comparison result as the control signal, wherein the clock generation circuit generates a signal having a frequency according to the control signal by oscillation and outputs the resultant signal, and the clock generation circuit, the phase comparison circuit and the low-pass filter constitute a phase locked loop (PLL).
With the above configuration, a multi-phase clock can be generated based on a clock synchronizing with the reference clock and having a stable frequency.
In the multi-phase clock transmission circuit described above, preferably, the clock generator further includes: a phase comparison circuit for comparing phases between the reference clock and the clock output from the clock generation circuit and outputting the comparison result; and a low-pass filter for outputting a low-frequency component of the comparison result as the control signal, wherein the clock generation circuit delays the reference clock in accordance with the control signal and outputs the resultant clock, and the clock generation circuit, the phase comparison circuit and the low-pass filter constitute a delay locked loop (DLL).
With the above configuration, a multi-phase clock can be generated based on a clock synchronizing with the reference clock and having the same frequency as the reference clock.
In the multi-phase clock transmission circuit described above, the delay element of the clock generation circuit and the plurality of delay elements of the delay circuit preferably have substantially the same configuration.
With the above configuration, the delay circuit can easily generate a signal substantially identical to the signal generated in the clock generator. In addition, with use of substantially the same delay elements, the design of the multi-phase clock generation circuit is simplified.
In the multi-phase clock transmission circuit described above, preferably, the clock is a differential signal, and the delay elements of the clock generation circuit and the delay circuit are differential buffers.
With the above configuration, the multi-phase clock can be obtained as a differential signal.
In the multi-phase clock transmission circuit described above, each of the plurality of delay elements of the delay circuit preferably controls the delay to be given to the input signal in accordance with a delay correction signal in addition to the control signal.
With the above configuration, the delay generated in each delay element of the delay circuit can be corrected with the delay correction signal. Therefore, by adjusting the delay to be equal to a delay generated in the delay element of the clock generation circuit, the phase difference between clocks constituting a multi-phase clock can be kept at a predetermined value. The power supply potential and the ground potential applied to the delay element of the clock generator may sometimes be different from those applied to the delay elements of the delay circuit in a circuit block depending on the positions of the components in an integrated circuit, for example. According to the present invention, even in such an event, the same delay can be generated in the delay elements of both the clock generator and the delay circuit.
Preferably, the delay circuit described above further includes a delay correction circuit receiving two signals among the signals output from the plurality of delay elements in cascade connection and the clock, for generating the delay correction signal in accordance with a difference between a phase difference between the received two signals and a predetermined value and outputting the delay correction signal.
With the above configuration, a delay generated in each delay element of the delay circuit can be automatically corrected in accordance with the phase difference between the two signals.
Preferably, the delay correction circuit outputs the delay correction signal as a digital signal.
With the delay correction signal being a digital signal, the configuration of the delay correction circuit can be simplified.
Preferably, the delay correction signal is input from outside a semiconductor integrated circuit including the multi-phase clock transmission circuit.
With the above configuration, a delay generated in each delay element of the delay circuit can be corrected easily for each chip from outside the semiconductor integrated circuit chip.
The multi-phase clock transmission circuit described above preferably further includes a buffer circuit corresponding to the delay circuit, wherein the buffer circuit changes the amplitude of the clock to a predetermined value and outputs the resultant clock to the corresponding delay circuit.
With the above configuration, a clock having a predetermined amplitude can be supplied to the delay circuit irrespective of the distance of transmission of the clock.
Preferably, the buffer circuit includes a delay element having substantially the same properties as the delay elements of the delay circuit.
With the above configuration, a clock output from the clock generator is supplied to the delay circuit as a signal having an amplitude substantially equal to that of the output signal of the delay element of the delay circuit. Therefore, the delays generated in the plurality of delay elements of the delay circuit can be made equal to each other, and thus the phase differences between the clocks constituting a multi-phase clock can be made equal to each other.
The multi-phase clock transmission circuit described above preferably further includes a buffer for changing the amplitude of an input signal to a predetermined value, the buffer being placed on a line for transmission of the clock at a position between a branch point for branching to the delay circuit and the clock generator.
With the above configuration, the amplitude of the clock transmitted can be kept at about a predetermined value.
Preferably, the buffer includes a delay element having substantially the same properties as the delay element of the clock generation circuit.
With the above configuration, the amplitude of the clock can be substantially kept at the amplitude of the signal output from the delay element of the clock generation circuit irrespective of the distance of transmission of the clock.
The multi-phase clock transmission circuit described above preferably further includes: an analog-digital conversion circuit for converting the control signal to a digital signal and outputting the resultant signal; and a digital-analog conversion circuit provided in correspondence with the delay circuit for converting the digitized transmitted control signal to an analog signal and outputting the resultant signal to the delay circuit.
With the above configuration, the control signal is prevented from changing during transmission to the delay circuit under influences of crosstalk and a variation of the power supply potential and the ground potential.
In the multi-phase clock transmission circuit described above, preferably, the delay circuit is provided in plural number, and the multi-phase clock transmission circuit further includes a plurality of phase interpolators placed in correspondence with the plurality of delay circuits, a line for transmission of the clock has a first portion from the clock generator to a turning point and a second portion from the turning point toward the clock generator, and has first and second branch points for branching to each of the phase interpolators in the first and second portions, respectively, each of the phase interpolators receives two signals via lines branching at the first and second branch points, changes the level of an output signal at substantially the midpoint between two timings at which the two signals respectively change the level, and outputs the resultant signal to the corresponding delay circuit as the clock, and the multi-phase clock transmission circuit is configured so that the times required for transmission of the signal through a line section between two adjacent branch points among the first branch points and a line section between the two branch points among the second branch points corresponding to the two adjacent first branch points are substantially equal to each other.
With the above configuration, the timings of clocks input into a plurality of delay circuits placed at some distance from each other can be made to match with each other. Therefore, a plurality of circuit blocks each having a delay circuit can use a multi-phase clock matching in timing.
The multi-phase clock transmission circuit described above preferably further includes a buffer or buffers of the same number on the line section between two adjacent first branch points and on the line section between the two second branch points corresponding to the two adjacent first branch points.
With the above configuration, the delay between two signals input into a phase interpolator is large. Therefore, the phase interpolator can easily generate an output signal of which the level changes at substantially the midpoint between the two timings at which the two signals respectively change the level.
Preferably, the length of the line section between two adjacent first branch points and the length of the line section between the two second branch points corresponding to the two adjacent first branch points are substantially equal to each other.
With the above configuration, the times required for transmission of a signal through the line section between two adjacent first branch points and through the line section between the two second branch points corresponding to the two adjacent first branch points can be made substantially equal to each other.
The multi-phase clock transmission method of the present invention includes the steps of: generating a clock synchronizing with a reference clock and a control signal responsive to a phase difference between the reference clock and the clock; and delaying a signal to obtain a multi-phase clock based on the clock and the control signal, wherein the step of generating a clock generates a signal having a frequency equal to an integral multiple of a frequency of the reference clock as the clock using a delay element for giving a delay according to the control signal to an input signal and outputting the resultant signal, and the step of delaying uses a circuit including a plurality of delay elements in cascade connection each giving a delay according to the control signal to an input signal and outputting the resultant signal, the circuit receiving the clock, and obtains signals output from the plurality of delay elements as signals constituting the multi-phase clock.